The present invention is directed to an integrated circuits (IC) and, more particularly, to a signal delay flip-flop cell for fixing a hold time violation.
In electronic circuits and data processing systems, clocked flip-flops are commonly used for propagating data through various data paths. Such flip-flops typically include master and slave latches using clock signals for receiving data inputs and propagating data within the IC in functional mode. Testability typically requires the flip-flops to be connectable, in scan test mode, into a serial scan chain for loading and unloading scan test signals (vectors).
Proper operation during either functional or test modes requires that the input data be captured before the data has changed again, before the set-up time of the flip-flop, and that the output of the flip-flop remain stable for a sufficient hold time for the next element in the IC to capture the data before the next clock phase. In modern systems, hold violations are most pervasive in data paths that have minimal logic between successive flip-flops. Serial scan chains are particularly susceptible to hold violations because there is little or no logic between the successive flip-flops.
ICs are designed using electronic design automation (EDA) tools. During the design flow, register-transfer-level (RTL) abstraction typically is used to create high-level representations of the IC, selecting standard cell designs and their characteristics from a standard cell library. The RTL description is typically converted to a gate-level description (such as a net-list) that can then be used by placement tools to create a physical layout. Placement is followed by clock tree synthesis (CTS) where distribution of clock signals is organized and problems of clock skew resolved.
Set-up time violations can often still be resolved even post-CTS. However, typically, hold time violations are a challenge, due to poor visibility of potential hold problems pre-CTS, while clock skew is not yet taken into account, and due to the design resources required to solve problems post-CTS. Conventionally, buffers have been added to slow data signals for problematic flip-flops, but at a penalty in terms of power consumption, chip area, and routing resources. The design problem arises only at the design stage of a product but the penalties are incurred throughout the life of the product.
It would be advantageous to have a way of resolving hold time problems efficiently, flexibly and with little or no penalty in terms of power consumption, chip area, and routing resources.